The present disclosure relates to a semiconductor memory device, and more particularly, to an apparatus for measuring an on-die termination (ODT) resistance, which can individually measure a resistance of a pull-up ODT unit and a resistance of a pull-down ODT in an ODT circuit and adjust them to the same value.
As the operating speed of semiconductor devices is increasing, a swing width of a signal interfaced between semiconductor devices is being gradually reduced for minimizing a delay time taken for signal transmission. However, due to the reduction in the swing width of the signal, the signal is greatly influenced by noise, causing impedance mismatching at an interface. The impedance mismatching may cause a difficulty in high-speed data transmission and distort output data. Since the impedance mismatching causes reflection of outgoing signals, there is a significant possibility that a transmission error will occur.
An impedance matching technology has been proposed which controls a resistance of a termination unit by adjusting the number of turned-on transistors among a plurality of transistors connected in parallel. This technology is called an on-chip termination or an on-die termination (ODT) and is applied to semiconductor memory devices of DDR-II or higher.
FIG. 1 illustrates a block diagram of a conventional ODT circuit.
Referring to FIG. 1, a pull-up/pull-down signal generator 1 generates first to n-th pull-up signals PU<1:n> and first to n-th pull-down signals PD<1:n>. When an ODT mode is set in a mode register set (MRS), at least one of the first to n-th pull-up signals PU<1:n> are enabled to a logic low level and at least one of the first to n-th pull-down signals PD<1:n> are enabled to a logic high level. At this point, the first pull-up signal PU<1> and the first pull-down signal PD<1> are simultaneously enabled, and the second pull-up signal PU<2> and the second pull-down signal PD<2> are simultaneously enabled. Likewise, the n-th pull-up signal PU<n> and the n-th pull-down signal PD<n> are simultaneously enabled.
First to n-th pull-up ODT units 2[1], 2[2], . . . , 2[n] are implemented with PMOS transistors and resistors and receive the first to n-th pull-up signals PU<1:n> to pull up a DQ terminal. First to n-th pull-down ODT units 3[1], 3[2], . . . , 3[n] are implemented with NMOS transistors and resistors and receive the first to n-th pull-down signals PD<1:n> to pull down the DQ terminal. Since the first pull-up signal PU<1> and the first pull-down signal PD<1> are simultaneously enabled, the first pull-up ODT unit 2[1] and the first pull-down OTD unit 3[1] are simultaneously turned on. Likewise, since the second pull-up signal PU<2> and the second pull-down signal PD<2> are simultaneously enabled, the second pull-up ODT unit 2[2] and the second pull-down ODT unit 3[2] are simultaneously turned on. Meanwhile, in order to make the signal outputted through the DQ terminal have half the power supply voltage (VDDQ), the resistance of the turned-on first pull-up ODT unit 2[1] and the resistance of the turned-on first pull-down ODT unit 3[1] must be equal to each other, and the resistance of the turned-on second pull-up ODT unit 2[2] and the resistance of the turned-on first pull-down ODT unit 3[2] must be equal to each other.
There is a need for improved ODT circuits.